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dec 2003 rev.0.3 g-link technology corp. 1 g-link advanced glt5640l32 cmos synchronous dram 2m x 32 sdram 512k x 32bit x 4banks synchronous dram g-link technology corporation glink reserves the right to change pr oducts or specification without notice. g-link technology corporation,taiwanweb : www.glink.com.tw email : sales@glink.com.tw tel : 886-2-26599658
dec 2003 rev.0.3 g-link technology corp. 2 g-link advanced glt5640l32 cmos synchronous dram operations bank/row activation ? 19 read operation ? 20 write operation ? 26 precharge ? 28 power-down ? 28 clock suspend ? 29 burst read/single write ? 29 concurrent auto precharge ? 30 read with auto precharge ? 30 write with auto precharge ? 31 timing waveforms initialize and load mode register ? 32 power-down mode ? 33 clock suspend mode ? 34 auto refresh mode ? 35 self refresh mode ? 35 read operations single read without auto precharge ? 36 read without auto precharge ? 37 read with auto precharge ? 38 alternating bank read accesses ? 39 read full-page burst ? 40 read dqm operation ? 41 write operations single write without auto precharge ? 42 write without auto precharge ? 43 write with auto precharge ? 44 alternating bank write accesses ? 45 write full-page burst ? 46 write dqm operation ? 47 memory part numbering ? 48 package dimensions ? 49 table of contents table of contents ? 2 device description & feature ? 3 pin assignment ? 4 pin description ? 5 absolute maximum rating ? 5 capacitance ? 6 dc characteristics & operating condition ? 6 ac operating condition ? 6 dc characteristics ? 7 ac characteristics-i ? 8 ac characteristics-ii ? 9 device operating option table ? 10 command truth table ? 11 functional block diagram ? 12 simplified state diagram ? 13 function description ? 14 initialization ? 14 register definition mode register ? 14 burst length ? 14 burst type ? 15 cas latency ? 16 operating mode ? 16 write burst mode ? 16 commands command inhibit ? 17 no operation (nop) ? 17 load mode register ? 17 active ? 17 read ? 17 write ? 17 precharge ? 17 auto precharge ? 18 burst terminate ? 18 auto refresh ? 18 self refresh ? 18
dec 2003 rev.0.3 g-link technology corp. 3 g-link advanced glt5640l32 cmos synchronous dram description the g-link glt5640l32 is a high speed 67,108,864bits cmos synchronous dram organized as 4 banks of 524,288 words x 32 bits. glt5640l32 is offering fully synchronous operation and is refer enced to a positive edge of the clock. all inputs and outputs a re synchronized with the rising edge of the clo ck input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. ordering information glt5640l32-5 glt5640l32 -5.5 glt5640l32 -6 glt5640l32 -7 glt5640l32 -8 glt5640l32 -10 200mhz 183mhz 166mhz 143mhz 125mhz 100mhz normal power part no. clock freq. power lvttl 86pin 400mil tsop-ii interface package 4 banks x 512k bits x 32 organization features ? jedec standard 3.3v power supply. ? auto refresh and self refresh. ? all device pins are compatible with lvttl interface. ? 4096 refresh cycle / 64ms. ? jedec standard 86pin 400mil tsop-ii with 0.5mm of pin pitch. ? programmable burst length and burst type. - 1, 2, 4, 8 or full page for sequential burst. - 4 or 8 for interleave burst. ? programmable cas latency : 2,3 clocks. ? all inputs and outputs referenced to the positive edge of the system clock. ? data mask function by dqm0,1,2 and 3. ? internal four banks operation. ? burst read single write operation. ? automatic precharge, includes concurrent auto precharge mode and controlled precharge
dec 2003 rev.0.3 g-link technology corp. 4 g-link advanced glt5640l32 cmos synchronous dram pin assignment (top view) vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 n.c vdd dqm0 /we /cas /ras /cs n.c ba0 ba1 a10/ap a0 a1 a2 dqm2 vdd n.c dq16 vssq dq17 dq18 vddq dq19 dq20 vssq dq21 dq22 vddq dq23 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 n.c vss dqm1 n.c n.c clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 vss n.c dq31 vddq dq30 dq29 vssq dq28 dq27 vddq dq26 dq25 vssq dq24 vss 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86pin tsop (ii) 0.5 mm pin pitch (400mil x 875mil)
dec 2003 rev.0.3 g-link technology corp. 5 g-link advanced glt5640l32 cmos synchronous dram pin descriptions absolute maximum rating parameter symbol rating unit ambient temperature ta 0~70 c storage temperature tstg -55~125 c voltage on any pin relative to vss vin,vout -1.0~4.6 v voltage on vdd relative to vss vdd, vddq -1.0~4.6 v short circuit output current ios 50 ma power dissipation pd 1 w pin clk cke ba0, ba1 a0~a10/ap ras, cas, we dqm0~3 dq0~dq31 vdd / vss vddq / vssq nc pin name system clock clock enable bank address address row address strobe, column address strobe, write enable data input / output mask data input / output power supply/ground data output power / ground no connection descriptions the system clock input. all other inputs are registered to the sdram on the rising edge clk controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh selects bank to be activated during ras activity selects bank to be read/written during cas activity row address : ra0~ra10, column address : ca0~ca7, auto-precharge flag : a10 controls output buffers in read mode and masks input data in write mode multiplexed data input / output pin power supply for internal circuits and input buffers power supply for output buffers no connection ras, cas and we define the operation refer function truth table for details cs chip select enable or disable all inputs except clk, cke and dqm
dec 2003 rev.0.3 g-link technology corp. 6 g-link advanced glt5640l32 cmos synchronous dram dc characteristics & operating condition (ta=0 to 70 c) parameter power supply voltage input high voltage input low voltage input leakage current output leakage current output high voltage output law voltage symbol vdd, vddq vih vil ili ilo voh vol min. 3.0 2.0 vssq-0.3 -1.0 -1.5 2.4 - typ. 3.3 3.0 0 - - - - max. 3.6 vddq+0.3 0.8 1.0 1.5. - 0.4 unit v v v ua ua v v note 1, 2 1, 3 1, 4 5 6 ioh = -2.0ma iol = +2.0ma notice : 1. all voltages are referenced to vss =0v 2. vdd/vddq(min) is 3.15v for glt5640l32-5/5.5/6 3. vih(max) is acceptable 5.6v ac pulse width with 3ns of duration with no input clamp diodes 4. vil(min) is acceptable ?2.0v ac pulse width with 3ns of duration with no input clamp diodes 5. vin = 0 to 3.6v, all other pins are not under test = 0 6. dout is disabled, vout=0 to 3.6v ac operating condtion (ta=0 to 70 c, 3.0v vdd 3.6v, vss=0v - note1) parameter ac input high / low level voltage input timing measurement reference level voltage input rise / fall time output timing measurement reference level symbol vih / vil v trip tr / tf v outref typ. 2.4 / 0.4 1.4 1 / 1 1.4 unit v v ns v note - - - - output load capacitance for access time measurement cl 30 pf 2 cl1 symbol cl2 cl/o input capacitance parameter data input / output capacitance clk pin a0~a10,ba0, ba1, cke, cs, ras, cas, we, dqm0~3 dq0~dq31 2.5 min 2.5 4.0 4.0 max 5.0 6.5 pf unit pf pf capacitance (ta=25 j, f=1mhz, vdd=3.3v)
dec 2003 rev.0.3 g-link technology corp. 7 g-link advanced glt5640l32 cmos synchronous dram dc characteristics (dc operating conditions unless otherwise noted) notice : 1. idd1 and idd4 depend on output loading and cycle rates. specified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3. glt5640l32-5/5.5/6/7/8/10 dc characteristics (dc operating conditions unless otherwise noted) parameter operating current test condition burst length = 1, one bank active tras tras(min), trp trp(min) iol = 0 ma speed note 5 -5.5 -6 -7 -8 -10 230 220 200 1800 170 150 1 precharge standby current in power-down mode cke vil(max), tck = 15ns cke vil(max), tck= ?? 2 2 - - precharge standby current in non power-down mode cke vih(min), cs vih(min), tck= 15ns input signals are changed on time during 2ckls all this pins vdd - 0.2 or 0.2v cke vih(min), tck= ?? input signals are stable 30 20 - - active standby current in power-down mode cke vil(max), tck = 15ns cke vil(max), tck= ?? 15 15 - - active standby current in non power-down mode cke vih(min), cs vih(min), tck=15ns input signals are changed on time during 2 clks all other pin vdd - 0.2v or 0.2v cke vih(min), tck= ?? input signals are stable 60 50 - - operating current (burst mode) tck tck(min) tras tras(min), iol = 0 ma all bank active 440 410 380 340 300 250 1 cl=3 cl=2 - - - - 250 200 trrc trrc(min) all banks active 2 operating current 190 180 250 240 220 200 self refresh current cke 0.2v 2 3 sym. idd1 idd2p idd2ps idd2n idd2ns idd3p idd3ps idd3n idd3ns idd4 idd5 idd6 ma unit ma ma ma ma ma ma ma ma ma ma ma
dec 2003 rev.0.3 g-link technology corp. 8 g-link advanced glt5640l32 cmos synchronous dram parameter ac characteristics - i (ac operating conditions unless otherwise noted) notice : 1. assume tr/tf (input rise and fall time) is 1ns. if tr & tf is longer than 1ns, transient time compensation should be considere d. 2. if clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter. 3. setup and hold time for data-input, address, cke and command pin -5 -5.5 -6 -7 -8 -10 clock pulse width input signal setup time input signal hold time clk to data output in low z-time system clock cycle time access time from clock clk to data output in high z-time cas latency = 3 cas latency = 2 cas latency = 3 cas latency = 2 cas latency = 3 cas latency = 2 sym. tck tck tclw tac tac tis tih tolz tohz tohz min 5.0 - 2.0 - - 1.5 1.0 1.0 - - max - 4.5 - - - - 4.5 - min 5.5 - 2.5 - - 1.5 1.0 1.0 - - max - 5.0 - - - - 5.0 - min 6.0 - 2.5 - - 1.5 1.0 1.0 - - max - 5.5 - - - - 5.5 - min 7.0 - 3.0 - - 1.75 1.0 1.0 - - max - 5.5 - - - - 5.5 - min 8.0 10.0 3.0 - - 2.0 1.0 1.0 - - max - 6.0 8.0 - - - 6.0 6.0 min 10.0 12.0 3.5 - - 2.5 1.0 1.0 - - max - 8.0 8.0 - - - 6.0 8.0 unit 1000 1000 1000 1000 1000 1000 ns clock high pulse width tchw 2.0 - 2.5 - 2.5 - 3.0 - 3.0 - 3.5 - data-out hold time toh 1.5 - 2.0 - 2.0 - 2.0 - 2.5 - 2.5 - note - 2 - 1 1, 3 1, 3 - 1 -
dec 2003 rev.0.3 g-link technology corp. 9 g-link advanced glt5640l32 cmos synchronous dram ac characteristics - ii (ac operating conditions unless otherwise noted) notice : 1. the minimum number of clock cycle is determined by dividing the minimum time required with clock cycle time and them rounding off to the next higher integer. 2. in case of row precharge interrupt, auto precharge and read burst stop. 3. a new command can be given trc after self refresh exit. ras cycle time precharge to data-out hi-z ns clk 1 - 2 -5 -5.5 -6 -7 -8 -10 parameter sym. min max min max min max min max min max min max unit note operation trc 55 55 60 70 70 70 auto refresh trrc 55 55 60 70 70 70 ras active time tras 40 100k 38.5 100k 42 100k 49 100k 48 100k 50 100k ras precharge time trp 15 - 16.5 - 18 - 20 - 20 - 20 - ras to ras bank active delay trrd 10 - 11 - 12 - 14 - 16 - 20 - cas to cas delay tccd 1 - 1 - 1 - 1 - 1 - 1 - data-in to precharge command tdpl 1 - 1 - 1 - 1 - 1 - 1 - data-in to active command tdal 4 - 4 - 4 - 4 - 4 - 4 - dqm to data-out hi-z tdqz 2 - 2 - 2 - 2 - 2 - 2 - dqm to data-in mask tdqm 0 - 0 - 0 - 0 - 0 - 0 - cas latency = 3 tproz 3 - 3 - 3 - 3 - 3 - 3 - cas latency = 2 tproz - - - - - - - - 2 - 2 - power down exit time tpde 1 - 1 - 1 - 1 - 1 - 1 - - self refresh exit time tsre 1 - 1 - 1 - 1 - 1 - 1 - 3 refresh time tref - 64 - 64 - 64 - 64 - 64 - 64 ms - - - - - - - ras to cas delay trcd 15 - 16.5 - 18 - 20 - 20 - 20 - mrs to new command tmrd 2 - 2 - 2 - 2 - 2 - 2 -
dec 2003 rev.0.3 g-link technology corp. 10 g-link advanced glt5640l32 cmos synchronous dram device operating option table 200mhz (5.0ns) glt5640l32-5 3 clks cas latency 3clks trcd 8clks tras 11clks trc 3clks trp 4.5 ns tac 1.5 ns toh 183mhz (5.5ns) 3 clks 3clks 7clks 10clks 3clks 5.0 ns 2.0 ns 166mhz (6.0ns) 3 clks 3clks 7clks 10clks 3clks 5.5 ns 2.0 ns 183mhz (5.5ns) 3 clks 3clks 7clks 10clks 3clks 5.0 ns 2.0 ns 166mhz (6.0ns) 3 clks 3clks 7clks 10clks 3clks 5.5 ns 2.0 ns 143mhz (7.0ns) 3 clks 3clks 7clks 10clks 3clks 5.5 ns 2.0 ns 166mhz (6.0ns) 3 clks 3clks 7clks 10clks 3clks 5.5 ns 2.0 ns 143mhz (7.0ns) 3 clks 3clks 7clks 10clks 3clks 5.5 ns 2.0 ns 125mhz (8.0ns) 3 clks 3clks 6clks 9 clks 3clks 6.0 ns 2.5 ns 143mhz (7.0ns) 3 clks 3clks 7clks 10clks 3clks 5.5 ns 2.0 ns 125mhz (8.0ns) 3 clks 3clks 6clks 9clks 3clks 6.0 ns 2.5 ns 100mhz (10.0ns) 2 clks 2clks 5clks 7clks 2clks 6.0 ns 2.5 ns 125mhz (8.0ns) 3 clks 3clks 6clks 9clks 3clks 6.0 ns 2.5 ns 100mhz (10.0ns) 2 clks 2clks 5clks 7clks 2clks 6.0 ns 2.5 ns 83mhz (12.0ns) 2 clks 2clks 4clks 6clks 2clks 6.0 ns 2.5 ns 100mhz (10.0ns) 3 clks 2clks 5clks 7clks 2clks 6.0 ns 2.5 ns 83mhz (12.0ns) 2 clks 2clks 5clks 7clks 2clks 6.0 ns 2.5 ns 2 clks 2clks 4clks 6clks 2clks 6.0 ns 2.5 ns glt5640l32-5.5 cas latency trcd tras trc trp tac toh GLT5640L32-6 cas latency trcd tras trc trp tac toh glt5640l32-7 cas latency trcd tras trc trp tac toh glt5640l32-8 cas latency trcd tras trc trp tac toh glt5640l32-10 cas latency trcd tras trc trp tac toh 66mhz (15.0ns)
dec 2003 rev.0.3 g-link technology corp. 11 g-link advanced glt5640l32 cmos synchronous dram command truth table read with autoprecharge command l cs l ras l cas l we x cken x dqm op code addr a10/ap ba - note l x x x l h h h x x x - no operation bank active l l h h x x ra - l h l h x x ca - l h read read with autoprecharge l h l h x x ca - l h write write with autoprecharge l l h l x x x - h l precharge all banks precharge selected bank burst stop l h h l x x x - dqm x v x - auto refresh l l l h h x x - self refresh l l l h l x x 1 entry h x x x h x 1 exit l h h h h x x x l x - exit l h h h h x x x h x - exit l h h h precharge power down x clock suspend x h x x - entry h x x x l x - exit l v v v notice : 1. exiting self refresh occurs by asynchronously bring cke from low to high. 2. x = don?t care, h = logic high, l = logic low, ba = bank address, ra = row address, ca = column address, op cpde = operand code, nop = no operation. h cken-1 h h h h h h h h h l h l l h v v v v x
dec 2003 rev.0.3 g-link technology corp. 12 g-link advanced glt5640l32 cmos synchronous dram functional diagram control logic command decoder column address buffer & burst counter clock generator clk cke row address buffer & refresh counter cs ras cas we mode register bank d row decoder sense amplifier column decoder and latch circuit bank c row decoder bank b row decoder bank a row decoder sense amplifier column decoder & latch circuit dq dqm address data control circuit latch circuit input & output buffer
dec 2003 rev.0.3 g-link technology corp. 13 g-link advanced glt5640l32 cmos synchronous dram cke cke idle row active self refresh cbr refresh power down active power down read write read a write a pre- charge read suspend read a suspend write suspend write a suspend power on mode register set precharge cke cke cke cke cke cke read write cke cke read write auto precharge write with auto precharge write with pre bst bst pre cke cke ref self self exit mrs pre(precharge termination) pre(precharge termination) automatic sequence manual input simplified state diagram
dec 2003 rev.0.3 g-link technology corp. 14 g-link advanced glt5640l32 cmos synchronous dram functional description in general, this 64mb sdram (512k x 32 x 4 banks) is a quad-bank dram that operates at 3.3v and in-cludes a synchronous interfac e (all signals are regis-tered on the positive edge of the clock signal, clk). each of the 16,777,216-bit banks is organized as 2,048 r ows by 256 columns by 32-bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and con-tinue for a programmed nu mber of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accesse d (ba0 and ba1 select the bank, a0-a10 select the row). the address bits (a0-a7) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the fo llowing sections provide detailed information covering device i nitialization, register defi-nition, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result i n undefined operation. once power is applied to vdd and vddq (simul ta-neously) and the clock is stable (stable clock is defined a s a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100ms delay prior to issuing any command o ther than a com-mand inhibit or a nop. starting at some point during this 100ms period and continuing at least through the end of this peri od, command inhibit or nop com-mands should be applied. once the 100ms delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is rea dy for mode register pro-gramming. because the mode register will power up in an unknown state, it should be loaded prior to apply ing any operational command. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 1. the bu rst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2 , 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the seq uential type. the full- page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should no t be used, as unknown operati on or incompatibility with future versions may result. when a read or wri te command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a7 when the bu rst length is set to two; by a2-a7 when the burst length is set to four; and by a3-a7 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the bou ndary is reached. register definition mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a bu rst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 1. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or inter-leaved), m4-m6 specify t he cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 is reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation.
dec 2003 rev.0.3 g-link technology corp. 15 g-link advanced glt5640l32 cmos synchronous dram burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type a nd is selected via bit m3. the ordering of accesses within a burst is deter-mined by the burst length, the burst type and the starting column address, as shown in table 1. m2 m1 m0 burst length m3 = 0 m3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved 1 0 0 reserved reserved 0 1 1 reserved reserved notice : 1. for a burst length of two, a1-a7 select the block-of-two burst; a0 selects the starting co lumn within the block. 2. for a burst length of four, a2-a7 select the lock-of-four burst; a0-a1 select the starting column within the block. 3. for a burst length of four, a3-a7 select the lock-of-four burst; a0-a2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0-a7 select the starting column 5. whenecer a boundart of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0-a7 select the unique column to be accessed, and mode register bit m3 is ignored. burst length 0>1>2>3>4>5>6>7 starting column address order of access within a burst type = sequential type = interleaved a0 2 0 1 a1 a0 4 0 0 8 0 1 1 0 1 1 a2 a1 a0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0>1>2>3>4>5>6>7 1>2>3>4>5>6>7>0 1>0>3>2>5>4>7>6 2>3>0>1>6>7>4>5 3>2>1>0>7>6>5>4 4>5>6>7>0>1>2>3 5>4>7>6>1>0>3>2 6>7>4>5>2>3>0>1 7>6>5>4>3>2>1>0 2>3>4>5>6>7>0>1 3>4>5>6>7>0>1>2 4>5>6>7>0>1>2>3 5>6>7>0>1>2>3>4 6>7>0>1>2>3>4>5 7>0>1>2>3>4>5>6 0>1>2>3 1>2>3>0 2>3>0>1 3>0>1>2 0>1>2>3 1>0>3>2 2>3>0>1 3>2>1>0 0>1 0>1 1>0 1>0 full page (256) n = a0 > a7 (location 0>256) c n , c n +1. c n +2, c n +3, c n +4? ?c n -1, c n ... not supported table 1. burst definition m3 0 1 burst type sequential interleave m6 m5 m4 cas latency reserved 0 0 0 1 0 0 1 0 1 0 2 0 1 1 3 1 1 1 reserved 1 0 1 reserved 1 0 0 reserved 1 1 0 reserved m9 0 1 burst type programmed burst length single location access m8 0 - m7 0 - m6 - m0 defined - operating mode standard operation all other states reserved *should program m10 = 0, to ensure compatibility with future device. figure 1. mode register definition mode register(mx ) reserved* wb op mode cas latency bt burst length 10 9 0 87654321 a10 a9 a0 a8 a7 a6 a5 a4 a3 a2 a1 address bus 0 0 ba0 ba1
dec 2003 rev.0.3 g-link technology corp. 16 g-link advanced glt5640l32 cmos synchronous dram cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first pie ce of output data. the atency can be set to one, two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycl e time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving aft er t1 and the data will be valid by t2, as shown in figure 2. table 2 below, figure 2. cas latency table 2. cas latency indicates the operating frequencies at which each cas latency setti ng can be used. reserved states should not be used as unknow n operation or incompatibility with futu re versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst len gth applies to read bursts, but write accesses are single-location (nonburst) accesses. clk command dq read nop dout t0 t1 t2 tlz toh tac cas latency=1 clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=2 t3 read clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=3 t3 nop t4 read don?t care undefined -7.0 cas latency = 1 50 cas latency = 2 100 cas latency =3 143 speed allowable operating frequency (mhz) -6.0 60 100 166 -8.0 40 100 125
dec 2003 rev.0.3 g-link technology corp. 17 g-link advanced glt5640l32 cmos synchronous dram commands command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0-a10. see mode register heading in the register definition sec-tion. the load mode reg ister command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0 and b a1 inputs selects the bank, and the address provided on inputs a0-a10 selects the row. this row remains active (or open) for accesses unt il a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0 and ba1 (b1) inputs selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not aut o precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if aut o precharge iis not selected, the row will remain open for subsequent accesses. read data appears on the dqs subject to the logic le vel on the dqm inputs two clocks earlier. if a given dqmx signal was registered high, the corresponding dqs will be high-z two clocks la ter; if the dqmx signal was registered low, the corresponding dqs will provide valid data. dqm0 corresponds to dq0-dq7, dqm1 corresponds to d q8- dq15, dqm2 corresponds to dq16-dq23 and dqm3 corresponds to dq24-dq31. write the write command is used to initiate a burst write access to an active row. the value on the ba0 and ba1 inputs selects the ba nk, and the address provided on inputs a0-a7 selects the starting column loca tion. the value on input a10 determines whether or not auto pr echarge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto prechar ge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array s ubject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed t o that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( trp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0 and ba1 select the bank. otherwise ba 0 and ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank.
dec 2003 rev.0.3 g-link technology corp. 18 g-link advanced glt5640l32 cmos synchronous dram auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write comma nd. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write com-mand. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue anoth er command to the same bank until the precharge time ( trp) is completed. this is determined as if an explicit precharge command wa s issued at the earliest possible time, as described for each burst type in the operation section of this data sheet. burst terminate the burst terminate command is used to truncate either fixed-length or full-page bursts. the most recently registered read or w rite command prior to the burst terminate command will be truncate d, as shown in the operation section of this data sheet. auto refresh auto refresh is used during normal operation of the sdram and is analagous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 64mb sdram requires 4,096 auto refresh cycles every 64ms ( tref), regardless of width option. providing a distributed auto refresh command every 15.625 s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( trc), once every 64ms. self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the s elf refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh comm and except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cyc les. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinit e period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defined as a signal cycling within timing con-straints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop c ommands issued (a minimum of two clo cks) for txsr because time is required for the co mpletion of any internal refresh in progress.
dec 2003 rev.0.3 g-link technology corp. 19 g-link advanced glt5640l32 cmos synchronous dram operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated. see figure 4. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the trcd specific ation. trcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge af ter the active command on which a read or write co mmand can be issu ed. for example, at rcd specificat ion of 20ns with a 125 mhz clock ( 8ns period) results in 2.5 clocks, r ounded to 3. th is is reflected in figure 3, which covers any case where 2 < t rcd (min)/tck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a diff erent row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between suc cessive active commands to the same bank is defined by trc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction o f total row-access over-head. the minimu m time interval between successive active co mmands to different ban ks is defined by trrd. figure 3. example : meeting trcd(min) when 2 < trcd(min)/tck 3 figure 4. activating a specific row in a specific bank clk nop t0 t1 t2 t3 active don?t care nop read or write trcd(min) +0.5 tck trcd(min)* tck tck tck * trcd(min) = 20ns, tck = 8ns trcd(min) x tck where x = number of clocks to be true. command don?t care clk cke cs# ras# cas# we# a0 - a10 ba0, ba1 row address bank address high
dec 2003 rev.0.3 g-link technology corp. 20 g-link advanced glt5640l32 cmos synchronous dram read operation read bursts are initiated with a read command, as shown in figure 5. the starting column and bank addresses are pro-vided with the read command, and autoprecharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the following illustrations, auto p recharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cas latency aft er the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 6 shows general timing for each possible cas latency setting. figure 5. read command figure 6. cas latency upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a full-page burst will contin ue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncated with a subsequent read command, and data from a fixed-length read burst may be immedi ately followed by data from a read command. in either case, a continu-ous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. clk command dq read nop dout t0 t1 t2 tlz toh tac cas latency=1 clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=2 t3 read clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=3 t3 nop t4 read don?t care undefined don?t care clk cke high cs# cas# ras# we# ba0, 1 bank address a0 - a7 column address a8, a9 a10 enable auto precharge disable auto precharge
dec 2003 rev.0.3 g-link technology corp. 21 g-link advanced glt5640l32 cmos synchronous dram this is shown in figure 7 for cas latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. this 64mb sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. figure 7. consecutive read bursts clk command t0 address read nop nop nop read nop bank, col n bank, col b dq dout, n dout, n+1 dout, n+2 dout, n+3 dout, b cas latency = 1 t1 t2 t3 t4 t5 x = 0 cycles clk command t0 address read nop nop nop read nop bank, col n bank, col b dq dout, n dout, n+1 dout, n+2 dout, n+3 dout, b cas latency = 2 t1 t2 t3 t4 t5 t6 nop x = 1 cycles clk command t0 address read nop nop nop read nop bank, col n bank, col b dq dout, n dout, n+1 dout, n+2 dout, n+3 dout, b cas latency = 3 t1 t2 t3 t4 t5 t6 nop x = 2 cycles t7 nop notice : each read command may be to either bank. dqm is low don?t care
dec 2003 rev.0.3 g-link technology corp. 22 g-link advanced glt5640l32 cmos synchronous dram clk command t0 address read read read read nop bank, col n dq dout n dout a dout x dout m cas latency = 1 t1 t2 t3 t4 bank, col a bank, col x bank, col m clk command t0 address read read read read nop nop bank, col n dq dout n dout a dout x dout m cas latency = 2 t1 t2 t3 t4 t5 bank, col a bank, col x bank, col m clk command t0 address read read read read nop nop bank, col n dq dout n dout a dout x dout m cas latency = 3 t1 t2 t3 t4 t5 t6 nop notice : each read command may be to either bank. dqm is low don?t care bank, col a bank, col x bank, col m figure 8. random read access a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 8, or each subsequent read may be performed to a different bank.
dec 2003 rev.0.3 g-link technology corp. 23 g-link advanced glt5640l32 cmos synchronous dram data from any read burst may be truncated with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a write command (subject to bus turn-around limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avo ided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. i n this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figures 9 and 10. the dqm signal must be asserted (high) at least tw o clocks prior to the write command (dqm latency is two clocks for output buff-ers) to suppress data-out from the read. once the write co mmand is registered, the dqs will go high-z (or re main high-z), regardless of the state of the dqm signal; provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in figure 10, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be deasserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the w ritten data is not masked. figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cy cle, and figure 10 shows the case where the additional nop is needed. clk command t0 address read nop nop nop write bank, col n dq dout n din b t1 t2 t3 t4 bank, col b dqm tck thz tds notice : a cas latency of three is used for illustration. the read command may be to any bank,and the write command may be to any bank. if a burst of one is used, then dqm is not required. notice : a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. command don?t care clk t0 address read nop nop nop write bank, col n dq dout n din b t1 t2 t3 t4 bank, col b dqm thz tds t5 nop figure 9. read to write figure 10. read to write with extra clock cycle
dec 2003 rev.0.3 g-link technology corp. 24 g-link advanced glt5640l32 cmos synchronous dram a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti-vated), and a full-page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 11 for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. note t hat part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst bein g executed to completion, a precharge command issued at the optimum time (as described above) provides the same clk command t0 address read nop nop nop precharge nop bank a, col n bank (a or all) dq dout n dout n+1 dout n+2 dout n+3 cas latency = 1 t1 t2 t3 t4 t5 t6 t7 nop active trp bank a, row x = 0 cycles clk command t0 address read nop nop nop precharge nop bank a, col n bank (a or all) dq dout n dout n+1 dout n+2 dout n+3 cas latency = 2 t1 t2 t3 t4 t5 t6 t7 nop active trp bank a, row x = 1 cycle notice : dqm is low don?t care clk command t0 address read nop nop nop precharge nop bank a, col n bank (a or all) dq dout n dout n+1 dout n+2 dout n+3 cas latency = 3 t1 t2 t3 t4 t5 t6 t7 nop active trp bank a, row x = 2 cycle figure 11. read to precharge
dec 2003 rev.0.3 g-link technology corp. 25 g-link advanced glt5640l32 cmos synchronous dram operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 12 for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. clk command t0 address read nop nop nop burst terminate nop bank, col n dq dout n dout n+1 dout n+2 dout n+3 cas latency = 1 t1 t2 t3 t4 t5 t6 nop x = 0 cycles clk command t0 address read nop nop nop burst terminate nop bank, col n dq dout n dout n+1 dout n+2 dout n+3 cas latency = 2 t1 t2 t3 t4 t5 t6 nop x = 1 cycle notice : dqm is low don?t care clk command t0 address read nop nop nop burst terminate nop bank a, col n dq dout n dout n+1 dout n+2 dout n+3 cas latency = 3 t1 t2 t3 t4 t5 t6 t7 nop nop x = 2 cycle figure 12. terminating a read burst
dec 2003 rev.0.3 g-link technology corp. 26 g-link advanced glt5640l32 cmos synchronous dram write operation write bursts are initiated with a write command, as shown in figure 13. the starting column and bank addresses are provided wit h the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write comman d. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, as suming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see figure 14). a f ull-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data for any write burst may be truncated with a subsequent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous clk cke cs# ras# cas# we# a0 - a7 column address high a8, a9 a10 enable auto precharge disable auto precharge ba0, 1 bank address clk command t0 address write nop nop nop dq t1 t2 t3 bank, col n din n din n+1 notice : burst length = 2. dqm is low clk command t0 address write nop write dq t1 t2 bank, col n din n din n+1 notice : dqm is low. each write command may be to any bank bank, col b din b don?t care figure 13. write command figure 15. write to write figure 14. write burst write command, and the data provided coincident with the new command applies to the new command. an example is shown in figure 15. data n + 1 is either the last of a burst of two or the last desired of a longer burst. this 64mb sdram uses a pipelined architecture a nd therefore does not require the 2n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 16, or each subsequent write may be performed to a different bank.
dec 2003 rev.0.3 g-link technology corp. 27 g-link advanced glt5640l32 cmos synchronous dram data for any write burst may be truncated with a subsequent read command, and data for a fixed-length write burst may be immedia tely followed by a read command. once the read command is regis-tered, the data inputs will be ignored, and writes will not be execut ed. an example is shown in figure 17. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be fol-lowed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at wh ich the last desired input data element is registered. the ?t wo-clock? write-back requires at least one clock plus time, regardless of frequency, clk command t0 address write write write write dq t1 t2 t3 bank, col n din n din a notice : each write command may be to any bank. dqm is low. bank, col a bank, col x bank, col m din x din m notice : the write command may be to any bank, and the read command may be to any bank. dqm is low. cas latency = 2 for illustration. t0 t1 t2 t3 t4 t5 clk write nop read nop nop nop command bank, col n address bank, col b din n dq din n+1 dout b dout b+1 don?t care notice : dqm could remain low in this example if the write burst is a fixed length of two . t0 t1 t2 t3 t4 t5 clk t6 twr = 1 clk (tck = twr) dqm trp command write nop nop nop precharge active nop address bank a, col n bank (a or all) bank a, row twr din n dq din n+1 twr = 2 clk (when twr > tck) dqm trp command write nop nop nop precharge active nop address bank a, col n bank (a or all) bank a, row twr din n dq din n+1 figure 17. write to read figure 16. random write cycle figure 18. write to precharge in auto precharge mode. in addition, when truncating a write burs t, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 18. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be iss ued until trp is met. the precharge will actually begin coincident with the clock-edge (t2 in figure 18) on a ?one-clock? twr and somet ime between the first and second clock on a ?two-clock? twr (between t2 and t3 in figure 18.) in the case of a fixed-length burst being execu ted to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result f rom the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts.
dec 2003 rev.0.3 g-link technology corp. 28 g-link advanced glt5640l32 cmos synchronous dram fixed-length or full-page write bursts can be trun-cated with the burst terminate command. when truncating a write burst, the in put data applied coin-cident with the burst terminate command will be ignored. the last data written (provided that dqm is low at tha t time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 19, where data n is the last desired data element of a longer burst. clk cke cs# ras# cas# we# high a0 - a9 a10 all banks bank selected ba0, 1 bank address clk command t0 address write burst terminate next command dq t1 t2 bank, col n din n notice : dqm is low. (address) (data) don?t care clk cle tcks tcks input buffers gated off enter power-down mode. exit power-down mode. trcd tras trc active nop nop don?t care all banks idle command precharge the precharge command (figure 20) is used to deactivate the open row in a particular bank or the open row in all banks. the ban k(s) will be available for a subsequent row access some specified time ( trp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0 and ba1 select the b ank. when all banks are to be precharged, inputs ba0 and ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle s tate and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress (see figur e 21). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when th ere is a row active in either bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buff ers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh peri od (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting tcks). figure 20. precharge command figure 19. terminating a write burst figure 21. power-down
dec 2003 rev.0.3 g-link technology corp. 29 g-link advanced glt5640l32 cmos synchronous dram clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivat ed, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is sus-pended. any command or data present on the input pins at the time of a suspended internal cl ock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figures 22 and 23.) clock suspend mode is exited by registering cke high ; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a logic 1. in th is mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). figure 22. clock suspend during write burst notice : for this example, burst length = 4 greater, and dqm is low. t0 t1 t2 t3 t4 t5 clk write nop nop nop command bank, col n address din n dq din n+1 cke internal clock din n+2 notice : for this example, cas latency = 2, burst length = 4 or greater, and dqm is low. t0 t1 t2 t3 t4 t5 clk read nop nop nop command bank, col n address dout n dq dout n+1 cke internal clock dout n+2 t6 nop nop dout n+2 don?t care figure 23. clock suspend during read burst
dec 2003 rev.0.3 g-link technology corp. 30 g-link advanced glt5640l32 cmos synchronous dram concurrent auto precharge an access command to (read or write) another bank while an access command with autoprecharge enabled is executing is not allowed by sdrams, unless the sdra m supports concurrent auto precharge. sdrams s upport co ncurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 24). 2. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contenti on. the precha rge to bank n will begin when the write to bank m is registered (figure 25). figure 24. read with auto precharge interrrupted by a read figure 25. read with auto precharge interrrupted by a write notice : dqm is low. t0 t1 t2 t3 t4 t5 clk nop read - ap bank n nop command address t7 t6 nop nop read - ap bank m nop nop page active read with burst of 4 interrupt burst, precharge idle bank n trp - bank n page active read with burst of 4 bank n, col a bank m, col d dout a + 1 dout a dout d + 1 dout d dq cas latency=3 (bank n) cas latency=3 (bank m) bank m internal states trp-bank m precharge don?t care notice : dqm is high at t2 to prevent dout-a+1 from contending with din-d at t4. t0 t1 t2 t3 t4 t5 clk nop read - ap bank n nop command address t7 t6 nop nop read - ap bank m nop nop page active read with burst of 4 interrupt burst, precharge idle bank n trp - bank n page active read with burst of 4 bank n, col a dout a dq cas latency=3 (bank n) bank m internal states write-back bank m, col d 1 dqm din d din d+1 din d+2 din d+3 twr-bank m
dec 2003 rev.0.3 g-link technology corp. 31 g-link advanced glt5640l32 cmos synchronous dram write with auto precharge 3. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after twr is met, where twr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 26). 4. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after twr is met, where twr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 27). figure 26. write with auto precharge interrrupted by a write figure 27. write with auto precharge interrrupted by a read notice : dqm is low. t0 t1 t2 t3 t4 t5 clk nop write-ap bank n nop command address t7 t6 nop nop read-ap bank m nop nop page active write with burst of 4 interrupt burst, write-back precharge bank n twr-bank n page active read with burst of 4 bank n, col a bank m, col d cas latency=3 (bank m) bank m internal states trp-bank m trp-bank n din a din a+1 dout d dout d+1 dq don?t care notice : dqm is low. t0 t1 t2 t3 t4 t5 clk nop write-ap bank n nop command address t7 t6 nop nop write-ap bank m nop nop page active write with burst of 4 interrupt burst, write-back precharge bank n twr-bank n page active write with burst of 4 bank n, col a dq bank m internal states write-back bank m, col d trp-bank n twr-bank m din d din d+1 din d+2 din d+3 din a din a+1 din a+2
dec 2003 rev.0.3 g-link technology corp. 32 g-link advanced glt5640l32 cmos synchronous dram timing waveforms initialize and load mode register notice : 1 the mode register may be loaded prior to the auto refresh cycles if desired. 2 outputs are guaranteed high-z after command is issued. clk command cke t0 t1 t n+1 t o+1 t p+1 t p+2 t p+3 tcks tckh tck tchw tclw tis tih tis tih nop precharge tis tih auto refresh nop nop auto refresh nop nop load mode refresh nop active dqm 0-3 code tih tis row a0 - a9 all banks code row tih tis single bank a10 bank all banks ba0 high-z t = 100us (min) trp trc trc tmrd power-up : vdd and clk stable precharge all banks auto refresh auto refresh program mode register 1, 2 don?t care undefined dq
dec 2003 rev.0.3 g-link technology corp. 33 g-link advanced glt5640l32 cmos synchronous dram power-down mode 1 notice : 1 violating refresh requirements during power-down may result in a loss of data. clk command cke t0 t1 t 2 t n+1 t n+2 tis tih tck tchw tis tih precharge nop nop nop active dqm 0-3 row a0 - a9 all banks row single bank a10 bank bank(s) ba0 high-z two clock cycles input buffers gated off while in all banks idle precharge all active banks exit power-down mode don?t care undefined dq tclw tis tis tih all banks idle, enter power-down mode power-down mode
dec 2003 rev.0.3 g-link technology corp. 34 g-link advanced glt5640l32 cmos synchronous dram clock suspend mode 1 notice : 1 for this example, the burst le ngth = 2, the cas latency = 3, and auto precharge is disabled. 2 a8 and a9 = ? don?t? care.? clk command cke t0 t1 t 2 t 6 t7 t 8 tis tih tck tchw tclw tis tih read nop nop nop nop write dqm 0-3 column e 2 a0 - a9 a10 ba0 don?t care undefined dq t3 t4 t 5 t 9 tclw tis tih nop nop tis tih column m 2 tih tis tih tis tih tis bank bank tolz tac dout m toh tac tohz dout m+1 tis tih dout e dout e+1
dec 2003 rev.0.3 g-link technology corp. 35 g-link advanced glt5640l32 cmos synchronous dram auto refersh mode t0 t1 t n+1 t n+1 t o+1 tis tih tck tchw tclw tis tih precharge nop auto refresh nop nop auto refresh nop nop active row all banks row single bank high-z trp trc trc precharge all active banks don?t care clk command cke dqm 0-3 a0 - a9 a10 ba0, ba1 dq bank(s) tis tih bank self refersh mode t0 t1 t2 t n+1 t o+2 tis tih tck tchw tis tih precharge nop auto refresh nop auto refresh all banks single bank high-z trp tsre precharge all active banks don?t care bank(s) tis tih tclw t o+1 tis tih tis clk command cke a0 - a9 a10 ba0, ba1 dq dqm 0-3 enter self refresh mode clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base)
dec 2003 rev.0.3 g-link technology corp. 36 g-link advanced glt5640l32 cmos synchronous dram notice : 1 for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by ?manual? precharge. 2 a8 and a9 = ? don?t? care.? read operations signal read, withou t auto precharge 1 don?t care undefined t0 t1 t 2 t 3 t 4 tis tih tck tchw tis tih active nop read precharge active nop row clk command cke dqm / dqml, dqmh a0 - a9 a10 ba0,ba1 dq tclw t 5 tis tih row column m 2 tis tih row row tis tih all banks single bank disable auto precharge bank bank bank bank tis tih doutm tac toh tohz tolz trcd tras trc cas latency trp
dec 2003 rev.0.3 g-link technology corp. 37 g-link advanced glt5640l32 cmos synchronous dram read, without auto precharge 1 notice : 1 for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by ?manual? precharge. 2 a8 and a9 = ? don?t? care.? don?t care undefined t0 t1 t 2 t 6 t7 t 8 tis tih tck tchw tclw tih tis active nop read nop nop nop precharge nop active row row bank trcd cas latency t3 t4 t 5 tis tih row row tis tih tis tih row tis tih column m 2 all banks single bank code bank bank disable auto precharge clk command cke dqm 0-3 a0 - a9 a10 ba0,ba1 dq d out m d out m + 1 d out m + 2 d out m + 3 tras trc tac toh tac toh tac toh tac tlz tohz trp
dec 2003 rev.0.3 g-link technology corp. 38 g-link advanced glt5640l32 cmos synchronous dram read, with auto precharge 1 notice : 1 for this example, the burst le ngth = 4, the cas latency = 2. 2 a8 and a9 = ? don?t? care.? don?t care undefined clk command cke read nop active nop nop nop nop active nop t0 t1 t 2 t 4 t 6 tis tih tck tchw tclw tis tih dqm 0-3 tih tis a0 - a9 a10 bank ba0,ba1 dq tclw t 3 t 5 t 7 t 8 tis tih row columnm 2 row tih tis row row enable auto precharge bank bank doutm dout m+1 dout m+2 dout m+3 tih tis trcd tras trc cas latency tac tac tac tac toh toh toh toh tohz trp tolz
dec 2003 rev.0.3 g-link technology corp. 39 g-link advanced glt5640l32 cmos synchronous dram alternating bank read access 1 notice : 1 for this example, the burst le ngth = 4, the cas latency = 2. 2 a8 and a9 = ? don?t? care.? clk command cke read nop active active nop read nop active nop t0 t1 t 2 t 4 t 6 tis tih tck tchw tis tih dqm 0-3 tih tis a0 - a9 a10 ba0,ba1 don?t care undefined dq tclw t 3 t 5 t 7 t 8 tis tih row columnm 2 row tih tis row row enable auto precharge d out m d out m+1 d out m+2 d out m+3 tih tis trcd - bank 0 tras - bank 0 trc - bank 0 cas latency - bank 0 tac tac tac tac toh toh toh toh trp - bank 0 tolz row columnb 2 row enable auto precharge bank 0 bank 0 bank 4 bank 4 bank 0 trrd trcd - bank 4 cas latency - bank 4 trcd - bank 0 d out b tac toh tac
dec 2003 rev.0.3 g-link technology corp. 40 g-link advanced glt5640l32 cmos synchronous dram read, full-page burst 1 notice : 1 for this example cas latency = 2. 2 a8 and a9 = ? don?t? care.? 3 page left open ; no trp. tih t0 t1 t 2 t 4 tis tih tck tch w tis tih tis clk command cke dqm 0-3 a0 - a9 a10 ba0,ba1 dq tclw t 3 t n+4 tis tih columnm 2 trcd cas latency tohz dout m tac tac tac toh tolz t5 t6 t n+1 tn+3 tn+2 active nop read nop nop nop nop nop burst term nop nop row tih tis row tis bank row dout m+1 dout m+2 dout m-1 dout m dout m+1 toh tac toh tac toh tac toh toh 256 locations within same row full-page burst does not self-terminate can use burst terminate command. 3 full-page completed don?t care undefined
dec 2003 rev.0.3 g-link technology corp. 41 g-link advanced glt5640l32 cmos synchronous dram read, dqm operation 1 notice : 1 for this example cas latency = 2. 2 a8 and a9 = ? don?t? care.? bank clk command cke read nop active nop nop nop nop nop nop t0 t1 t 2 t 4 t 6 tis tih tck tchw tis tih dqm 0-3 tih tis a0 - a9 a10 ba0,ba1 don?t care undefined dq tclw t 3 t 5 t 7 t 8 tis tih row columnm 2 tih tis row tih tis trcd cas latency tac tac tac toh toh toh tolz enable auto precharge disable auto precharge bank dout m tohz dout m+2 tolz dout m+3 tohz
dec 2003 rev.0.3 g-link technology corp. 42 g-link advanced glt5640l32 cmos synchronous dram write operations single write, without auto precharge 1 notice : 1 for this example, the burst length = 4, and the write burst is followed by a ?manual? precharge. 2 10ns is required between and the precharge command, regar dless of frequenct, to meet twr. 3 a8 and a9 = ?don?t care.? write nop active precharge nop active nop t0 t1 t 2 t4 t 6 tis tih tck tchw tis tih row row trcd twr 2 trp don?t care clk command cke dqm / dqml, dqmh a0 - a9 a10 ba0,ba1 dq bank(s) tis tih bank tclw t 3 t5 tis tih row column m 3 row tis tih tis tih all banks single bank disable auto precharge bank bank din m tis tih tras trc
dec 2003 rev.0.3 g-link technology corp. 43 g-link advanced glt5640l32 cmos synchronous dram write, without auto precharge 1 notice : 1 for this example, the burst length = 4, and the write burst is followed by a ?manual? precharge. 2 faster frequencies require two clocks (when twr > tck). 3 a8 and a9 = ?don?t care.? tih t0 t1 t 2 t 4 tis tih tck tchw tis tih tis tclw t 3 tis tih columnm 3 trc trp t5 t6 t7 t8 active nop write nop nop nop precharge nop active row tih tis row tis bank row don?t care row row bank d in m+3 d in m+2 d in m+1 d in m clk command cke dqm 0-3 a0 - a9 a10 ba0,ba1 dq tras trcd twr 2 tis tih tis tih tis tih tis tih enable auto precharge tih all banks single bank bank
dec 2003 rev.0.3 g-link technology corp. 44 g-link advanced glt5640l32 cmos synchronous dram write, with auto precharge 1 notice : 1 for this example, the burst length = 4. 2 faster frequencies require two clocks (when twr > tck). 3 a8 and a9 = ?don?t care.? tih t0 t1 t 2 t 4 tis tih tck tch w tis tih tis tclw t 3 tis tih columnm 3 trc trp t5 t6 t7 t9 t8 active nop write nop nop nop nop nop nop active row tih tis row tis bank row don?t care row row row d in m+3 d in m+2 d in m+1 d in m clk command cke dqm 0-3 a0 - a9 a10 ba0,ba1 dq tras trcd twr 2 tis tih tis tih tis tih tis tih enable auto precharge tih
dec 2003 rev.0.3 g-link technology corp. 45 g-link advanced glt5640l32 cmos synchronous dram alternating bank write access 1 notice : 1 for this example, the burst length = 4. 2 faster frequencies require two clocks (when twr > tck). 3 a8 and a9 = ?don?t care.? tih t0 t1 t 2 t 4 tis tih tck tch w tis tih tis tclw t 3 tis tih column m 3 trc - bank 0 trp - bank 0 t5 t6 t7 t9 t8 active nop write nop active nop write nop active row tih tis row tis don?t care row row d in m+2 d in m+1 d in m clk command cke dqm 0-3 a0 - a9 a10 ba0,ba1 dq tras - bank 0 trcd - bank 0 twr 2 -bank 0 tis tih tis tih tis tih d in m+3 tis tih enable auto precharge nop row column b 3 row enable auto precharge tih bank 0 bank 0 bank 1 bank 1 bank 0 d in b tis tih d in b+1 tis tih d in b+2 tis tih d in b+3 tis tih trcd - bank 0 trcd - bank 4 twr - bank 4 trrd
dec 2003 rev.0.3 g-link technology corp. 46 g-link advanced glt5640l32 cmos synchronous dram write, full-page burst 1 notice : 1 a8 and a9 = ?don?t care.? 2 twr must be satisfied prior to precharge command. 3 page left open ; no trp. clk command cke write nop active nop nop nop nop nop burst term t0 t1 t 2 t 4 t n+1 tis tih tcl tchw tis tih dqm 0-3 tih tis a0 - a9 a10 ba0,ba1 don?t care tcke t 3 t 5 t n+2 t n+3 tis tih row columnm 1 tih tis row trcd 256 locations within same row bank bank tih tis dq din m din m+2 din m+1 din m-1 din m+3 tih tis tih tis tih tis tih tis tih tis full page completed full page burst does not self-terminate. can use burst terminate command to stop. 2,3
dec 2003 rev.0.3 g-link technology corp. 47 g-link advanced glt5640l32 cmos synchronous dram write, dqm operation 1 notice : 1 for this example, the burst length = 4. 2 a8 and a9 = ?don?t care.? write nop active nop nop nop nop t0 t1 t 2 t4 t 6 tis tih tck tchw tis tih row trcd don?t care clk command cke dqm 0 - 3 a0 - a9 a10 ba0,ba1 dq bank tis tih tclw t 3 t5 tis tih row column m 2 tis tih tis tih disable auto precharge bank din m tis tih t 7 nop enable auto precharge din m+2 tis tih din m+3 tis tih
dec 2003 rev.0.3 g-link technology corp. 48 g-link advanced glt5640l32 cmos synchronous dram glt 5 640 l 32 - 10 tc 4 : dram 5 : synchronous dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram 9 : sgram -sram 064 : 8k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo) 11 : 1m(c/fpm) 12 : 1m(h/edo) 13 : 1m(h/fpm) 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) 160 : 16m(edo) 161 : 16m(fpm) 640 : 64m(edo) 641 : 64m(fpm) -sdram 40 : 4m 160 : 16m 640 : 64m voltage blank : 5v l : 3.3v m : 2.5v n : 2.1v config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns sdram : 5 : 5ns/200 mhz 5.5 : 5.5ns/182 mhz 6 : 6ns/166 mhz 7 : 7ns/143 mhz 10 : 10ns/100 mhz package t : pdip(300mil) ts : tsop(type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp fg : 48pin bga 9x12 fh : 48pin bga 8x10 fi : 48pin bga 6x8 power blank : standard l : low power ll : low low power sl : super low power temperature range e : extended temperature i : industrial temperature blank : commercial temperature
dec 2003 rev.0.3 g-link technology corp. 49 g-link advanced glt5640l32 cmos synchronous dram package dimensions 86 pin tsop-ii 400mil plastic notice : dimension unit, milimeter(mil). detail - a detail - a 22.22 / typ. (875) detail - b 0.5 / typ. (20) 0.61 / typ. (24) 1.2 / max. (47) 0.10 detail - b 5w 5w 5] 5] 5|5?5?5?5p5?5?5?5?5?5?5?5?5?5?5p5s5?55?5^ 5|5?5?5?5p5?5?5?5?5?5?5?5?5?5?5p5s5?55?5^ 1 43 44 86 11.76 ?? 0.2 (463 ?? 8 ) 10.16 ?? 0.13 (400 ?? 5 ) 0.2 0.03 (8 1 ) 1.0 ?? 0.05 (39 ?? 2 ) 0.15 ?? 0.03 (6 ?? 1 ) 0.21 (8) 0.665 (26) 0.25 / typ . (10) gage plane 0.1 ?? 0.05 (4 ?? 2 ) 0.5 0.1 (20 4 ) 0.8 0.2 (32 7 ) ps. ? 7

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